What role does transistor T2 play in this constant voltage reference generator?

In a very rough explanation, T2 act as regulator.
When you power up the circuit T1 go ON, then there's a current that go in the branch R2-T1-R3 (call it \$I1\$), and then VRE is the voltage across R3 (R3*I1) plus the T1's \$V_{DS}\$.

If the Vcc go up, for example, the current \$I1\$ increase ⇒ increase the voltage across R3 ⇒ increase the current drawn by T2 ⇒ decrease the current \$I1\$ ⇒ decrease the voltage across R3.

In this system, T1 passes some current, and it's unimportant how much current, but the consequence of that current is a voltage across R3. This voltage is \$V_{GS}\$ for T2, and as you should know, \$V_{GS}\$ is what determines the "on" (or "off") state of a FET.

If T2 switches "on", it tends to connect T1's gate more closely to ground, 0V, directly reducing the \$V_{GS}\$ of T1, switching T1 more "off". This reduces R3 current and T2's \$V_{GS}\$. This then causes T2 to switch more "off", in opposition to the initial perturbation of T2's state.

This relationship forms negative feedback. The two transistors operate together to maintain a stable condition, in which both \$V_{GS}\$ setlle at exactly the value required to maintain that state. If either \$V_{GS}\$ were to change, even by the tiniest amount, this would cause the other \$V_{GS}\$ to change also, in a direction that would oppose the initial perturbation, and restore equilibrium.

In this way, currents in the system are held constant, and consequently \$VRE\$ is also constant. You could no doubt demonstrate that many nodes in this circuit have constant potential, not just \$VRE\$, but \$VRE\$ seems to be adjustable, by varying R1 and/or R2. It is negative feedback that produces constant and stable state, but resistances and FET \$V_{GS(TH)}\$ that determine the actual values of potentials and currents.

Of course, since \$V_{GS(TH)}\$ varies with temperature, potentials and currents are only as "constant" as temperature.

From the provided circuit, it is clear that the static VRE voltage, here indicated by Vo, is desired, as there are no signal sources. I therefore proceed with a static analysis of the circuit. It contains two N-channel enhancement MOSFETs, for which the analytical relationship between drain current and gate-source voltage VGS is known, given the threshold parameters KMOS and VGST.

This novel voltage reference was presented for sensing ferromagnetic RAM with a self-trimmed bias voltage reference Vre.

I ran it on Falstad's sim and found some novel properties.

1. Vre matches Vgs(th) of T1 plus the very low current and voltage drop across R2.
2. When R2 matches R3 then any noise in Vdd has a 98% reduction if both FETs are matched, which was the optimal R ratio point.
3. If T2 has a much lower Vgs(th) then the reduction is more than 99.6% reduced.

This puts both T1 and T2 into the saturation high resistance zone.

Read the Vpp levels.

In another simulation using R2/R1=50, I vary R3 and record Vref using V+=10V. But due to the heat loss at high Vref/V+, efficient low current occurs with low R3/R2 <<1 while R2/R1=50.