Can crystal loading capacitors be much larger than nominal if clock accuracy is not important?

Question

I've read several previous questions on this topic such as here and here with useful answers from Olin and Andy, respectively.

I am currently modernizing a design that used 2x 47 pF capacitors on a crystal with 18-22 pF nominal load capacitance. So accounting for various other contributions to the load capacitance according to the links above, the actually implemented load capacitance was probably above 30 pF, so far above nomimal. The product worked fine with no clock issues reported. MCU (Atmega) datasheet contains some info in sections 9.3, 9.4 and recommends a max. value of 22 pF for each of the two capacitors.

In Andy's answer linked above, it also appears that higher loading capacitance makes the oscillation more resilient, albeit at the expense of frequency accuracy. Is this really the case? Are there drawbacks (other than frequency inaccuracy) to placing capacitance substantially exceeding the nominal value, e.g. using 2x 100 pF for an effective load capacitance of around 60 pF?

I've tried simulating this with Qspice's native crystal element, but I cannot make complete sense of the results, which are reported below. The green curves are for 2x 100 pF. It appears to me that the phase curves indeed more clearly clip the -90° line, but I am not sure if more resilient oscillation is the correct interpretation.

Answer 1

Don't know what is meant by "more resilient".

Scaling-up those two feedback capacitors tends to raise Q, and makes the oscillator less susceptible to interfering local signals and stray coupling to adjacent circuits.

Downside: scaling-up feedback capacitors also raises crystal current, which means the crystal sees more power...quite possibly exceeding its power rating. In the usual inverter-type Pierce circuit a resistor is often specified at inverter output...which tends to limit the power seen by the crystal. Without this series resistor, the crystal is likely over-driven.

• Over-driving the crystal causes heat and drift.
• An over-driven crystal may oscillate at spurious resonant frequencies considerably-removed from fundamental frequency.

Answer 2

To a certain extent, yes, but as always, it depends on the chip and its oscillator design and other parameters of the crystal how well it will work.

For a chip with data sheet describing the oscillator parameters like transconductance, you can actually calculate a number for the margin of oscillation. For example, often a value of 5 and above means a good margin and oscillator is expected to start up and oscillate properly under all temperature and supply voltage conditions. Less than 5, not so great, and you likely need to select another crystal with less ESR and change the load capacitors to smaller value.

Higher capacitance will make other stray capacitances affect the frequency less so it is more stable in that sense. But higher capacitance than the crystal expects pulls the frequency down, and if you want to externally tune the frequency with variable capacitance, the crystal with lots of load will be less pullable.

There will also be more current flowing in larger capacitances so the crystal ESR dissipates more power, it could get overdriven and the waveform to be not very sinewavy and there are limits how much a crystal can handle power.

If you put 100pF caps to a MCU that limits max capacitor value to something like 22pF, it likely fails to work at all.