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SPI Buses with multiple devices often contain slaves with differing maximum clock speeds. The speed of the bus is often set by the speed of the slowest device.

In my application, I have a 100MHz shift register sharing the bus with a 30MHz ADC. To mimimize latency, I would like to clock the shift register at 100MHz while the ADC's chip select is de-asserted.

Is it possible / recommended to temporarily increase the bus speed past the limits of the slower device, provided that the slower device is disabled via its chip select pin?

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  • \$\begingroup\$ If a chip select really does what it's supposed to do, why wouldn't it be? \$\endgroup\$ Commented Jul 20, 2022 at 19:06

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Reset to default
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Of course it is possible. Unless depending on your specific devices if something prevents it, but usually nothing prevents it.

When a device is disabled by setting chip select high, it does not listen to the bus.

So you are free to change bus mode (clock polarity and phase) and speed to be suitable for the device you will talk to next.

If you would state which devices you have on the bus it could be confirmed if the devices work or not.

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