Questions tagged [cadence]
For anything related to Cadence: EDA Tools and IP for System Design Enablement
207 questions
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Advice on S Band RF GaN transistor with MWO libraries
I'm designing a microwave class F power amplifier, and I'd need a transistor in the 2.7-2.9 GHz range with at least 10 dB gain (16 dB would be ideal, but feel free to advice anything above that ...
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Filter Design on Cadence AWR
I have been trying to implement an order 5 Chebyshev LPF by using Kuroda's identity and Richard transformations to convert the standard circuit to microstrip lines and open stubs. This is the design I ...
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How cadence layout appears?
I'm having trouble creating a Virtuoso/Cadence layout. I know there are videos online that show it, but when I run the editor, it doesn't appear, as shown in the figure.
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Low-power hybrid comparator block diagram and transistor-level design (90nm CMOS)
I’m currently working on my final year major project titled “Design of Low Power Hybrid Comparator using 90nm CMOS Technology.”
Our goal is to design a comparator that combines the features of both ...
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ERROR (CMI-2675): PM3: The parameter `Xgl' = 0 m must be smaller than `Ldrawn * Lmlt + XL' = -13.499 nm
I was designing a PTAT circuit in cadence and im persistently getting this error. Ive designed many other circuits but have never faced this error. Where am i going wrong
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Dot product of 2 arrays in Verilog (MIPS32 Processor)
I am trying to write a testbench in Verilog for computing dot product of two arrays.
The base code for which the testbench has to be written is:
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Cadence Virtuoso: easiest fastest way to export and visualize plots in a clean way for thesis / report / paper
I need help to identify a method to export plots and graphs in a clean way from Virtuoso. I am writing my thesis and really tight on time. Exporting the images to vector graphs needs a lot of ...
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In DC analysis in Virtuoso, a variable is somehow being set to 0 but I don't understand why?
During DC analysis a variable is somehow being set to 0 and I don't understand why.
I've created a circuit of an inverting amplifier with a custom op-amp, in that custom op-amp I have multiple ...
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Why is my differential amp not getting any open-loop gain?
This is a follow up question from a previous question.
This is the schematic for my differential amplifier:
Here is the test bench for my AC simulation:
And here is the Bode plot of Vout/Vin:
And ...
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Why am I getting this simulation error in Cadence?
I am trying to make a differential amplifier with VCVS (voltage-controlled-voltage-sources). Here is my schematic:
I set up this AC simulation to see the open loop gain (the symbol "amp1" ...
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How do I characterise this NMOS in Cadence Virtuoso if I don't know its width?
The circuit is a simple one stage amplifier:
The whole amplifier (do not care about the numbers please, they might very well be wrong)
Relevant data:
Vdd= 1.8V
IMCR+= 1.6V
SR= 5v/us
From the SR, I ...
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How to Open a Cadence Allegro 16.3 .BRD File without Access to Full Software?
I’m working on a project involving Texas Instruments’ AM335x ICE Board, and I downloaded their .BRD file for the PCB layout. Unfortunately, this file was saved in Cadence Allegro version 16.3, and I ...
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Cadence SDF Annotator for a back-annotated simulation
I am trying to use the Cadence SDF Annotator for a gate-level back-annotated simulation. I am working with a simple 8-bit adder in order to familiarize myself with the design flow.
I am using the ...
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Cadance to Altium Conversion - Is it Hard?
Does anyone know how much work is required to convert Cadence PCB design files to Altium importable files? I've been told it's the equivalent of 2-3 months of work. I'm slightly dubious but I'm ...
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Standard Naming Convention for Cadence Files
This is a question regarding the naming of libraries and cellviews in the Cadence Design Systems' IC tool. While being somewhat company and work-culture dependent, I am wondering what naming ...
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