Questions tagged [verilog]
Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.
2,055 questions
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Read functionality issue in Receiver FSM for UART
I really want to understand if my implementation of UART receiver FSM in Verilog is correct or not. In my current implementation, the transmitter and receiver communicate with the baud clock, which ...
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JK flip flop behavior on startup in Verilog
I've tried to implement a JK flip flop in Verilog, but while testing, I found that whatever inputs of j and k I give on startup, until I reset the flip flop (j=0, k=1), the outputs will not be seen ...
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Why is the waveform not matching? (2 clock delay in FSM code)
Context : I have been tasked with testing a HC-04 Ultrasonic sensor with Verilog, and below is the Verilog code, the testbench and the waveform that I am getting,
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Trying to do both synthesis and simulation for iCE40 UP5K when using internal clock and LED driver, but can only get one or the other [closed]
Before putting in an order for an Upduino to take another stab at learning about FPGAs, I figured I'd get the toolchain (yosys and nextpnr) figured out first and work through some tutorials. This was ...
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Different outputs for RTL and gate level netlist simulations for a latch used in clock gating
I am trying to implement clock gating logic manually using a latch and an AND gate as shown in the figure.
The latch has an enable (en) and a done signal which are ...
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What to do when a Verilog state machine simulation doesn't reflect the signals?
I'm working on a Verilog project using ModelSim, and I've created a testbench to simulate the behavior of a module called Elevator_FSM, which models an elevator's operation.
My goal is to assign ...
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Analyzing unexpected output from Verilog bit unpacking and reassembly logic
I'm working on a Verilog task that rearranges bits from a 312-bit word into a new 312-bit format using 8-bit temporary storage (temp[39]). Below is a simplified ...
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How blocking assignment affect non-blocking assignment in Verilog?
module t;
reg a;
initial a <= #4 0;
initial a <= #4 1;
initial $monitor ($time,,"a = %b", a);
endmodule
Output of above Verilog code is:
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Interfacing ADS1115 ADC with Microchip PolarFire SoC Discovery Kit
I have been trying to connect the ADS1115 ADC with my Microchip PolarFire SoC discovery kit FPGA board, I have written the FSM for I2C master by collecting the code from various sources because I am ...
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Why is Vivado connecting this reset to the CE pin when the R pin is available?
Vivado is connecting up the reset signal through a LUT to the CE pin of the FDRE, even though the R pin is available. This is a 2k signal, and it's using up 2k LUTs to do this, unnecessarily. Any ...
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Is my Finite State Machine Moore or Mealy?
Can someone please tell me whether the following FSM that I designed is Moore or Mealy? It is a UART Transmitter.
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Must a `for` loop be within an `initial,always` block?
I got two errors when using Vivado.
module top;
reg i_clk;
always
begin
for (u=0;u<3;u=u+1)｛$display(" %d ",i_clk)｝
end
<...
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