Questions tagged [flipflop]
A flip-flop or latch is a circuit that has two stable states and can be used to store state information.
1,116 questions
0
votes
3
answers
67
views
How to find the setup and hold time for a T-FF built from a D-FF and XOR gate in feedback?
I have the following:
And I'm supposed to find the T_su, T_h of this block.
The thing is, I don't know how to deal with the feedback of Q into the XOR gate in the timing constraints.
I have for the D-...
- 417
0
votes
0
answers
114
views
How do these SPDT Relays Work to make a D-Type Flip-Flop? (And de-bouncing it)
What I want:
The functionality here is to use a momentary push button to latch a 12v relay on and off with succesive pushes.
I have access to the high side of the relay coil.
The relay powers the ...
- 29
1
vote
0
answers
137
views
12V Automotive Control with 5V Logic
Background
I'm working on a personal project to control auxiliary lights on the front of a car. The lights themselves are powered directly from the battery, and are switched on using standard ...
- 29
2
votes
1
answer
246
views
Why would the RCO be 9 on a binary counter? 74HC161
I am currently doing a question in a textbook and am supposed to be creating the WF’s for a 74HC161 and its Q outputs as well as the RCO. The RCO is going high at 9 which is also the LOAD, but ...
- 33
3
votes
2
answers
161
views
JK flip flop behavior on startup in Verilog
I've tried to implement a JK flip flop in Verilog, but while testing, I found that whatever inputs of j and k I give on startup, until I reset the flip flop (j=0, k=1), the outputs will not be seen ...
- 31
-1
votes
1
answer
131
views
FSM to latch first of three pulses and hold winner until reset - interview question [closed]
Interview Question:
I have a small “race” problem to implement as an FSM using D flip-flops only. There are three lanes. At the end of each lane there is a pushbutton circuit that outputs a clean one-...
- 335
0
votes
2
answers
230
views
How to derive an FSM from this timing diagram (clk, in, out)?
I have a timing diagram with clk, input, and output signals (see image above).
I was able to sketch a circuit implementation using flip-flops and logic gates,
but I am struggling to describe it as a ...
- 335
1
vote
2
answers
207
views
Clear and Preset in SR Flip Flop
I am new to learning sequential circuits and in a lecture I was taught about Preset and Clear. My doubt is that in a SR Flip Flop using NAND implementation and active low clear and Preset we should ...
- 113
0
votes
1
answer
112
views
JK flip-flop timing diagram: Multisim vs. Wikipedia
[Related: JK flip-flop timing diagram: is Wikipedia correct?]
I am trying to understand how the difference in the below timing diagrams comes about. The first one is from Wikipedia, the second one is ...
- 35
3
votes
2
answers
463
views
JK flip-flop timing diagram: is Wikipedia correct?
Reading up on some digital logic foundations, I had a look on the Wikipedia entry about the different types of latches and flip-flops. Specifically, I tried to understand the timing diagram for the JK ...
- 35
1
vote
1
answer
184
views
Designing a master–slave D flip‑flop with logic gates in Logisim: state‑table derivation and static-hazard problem
I’m trying to build a master–slave D flip‑flop from scratch with only logic
gates in Logisim.
My workflow so far:
Start from a behavioural model (2 FF D: I set the Master on High level and the Slave ...
- 193
3
votes
5
answers
692
views
How to find the signal that has the first rising edge
I'm working on creating a logic circuit that can detect which of the signals B and C have the first rising edge after a falling edge of signal A. The output should be low if B is first and high if C ...
- 71
3
votes
2
answers
353
views
Why does my 4-bit ripple counter in Logisim always start at 1111, and how do I make it start at 0000?
I’m trying to build a 4-bit asynchronous (ripple) counter in Logisim Evolution 2.7.1 using four T–Flip-Flops, but I can’t get it to start counting from 0000. Instead, as soon as I click the clock the ...
- 1
3
votes
1
answer
367
views
How to build a proper Master-Slave T Flip-Flop using D Flip-Flops in Logisim?
I’m trying to correctly build a T Flip-Flop using a Master-Slave configuration in Logisim 2.7.1 win.
What I want:
I want to understand how to build a real T Flip-Flop using two D Flip-Flops connected ...
- 1
3
votes
1
answer
145
views
Trouble implementing a T Flip-Flop (Master-Slave) in Logisim: output not toggling
I’m trying to design a T Flip-Flop using a Master-Slave configuration in Logisim 2.7.1 win.
I want to understand how to correctly build a T Flip-Flop using D Flip-Flops and an XOR gate.
What I’m doing:...
- 1