Questions tagged [system-verilog]
In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.
549 questions
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Read functionality issue in Receiver FSM for UART
I really want to understand if my implementation of UART receiver FSM in Verilog is correct or not. In my current implementation, the transmitter and receiver communicate with the baud clock, which ...
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Use of new constructor in extended classes from uvm base classes
Code link: [https://edaplayground.com/x/9cte]
For the below code
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JK flip flop behavior on startup in Verilog
I've tried to implement a JK flip flop in Verilog, but while testing, I found that whatever inputs of j and k I give on startup, until I reset the flip flop (j=0, k=1), the outputs will not be seen ...
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Why is the waveform not matching? (2 clock delay in FSM code)
Context : I have been tasked with testing a HC-04 Ultrasonic sensor with Verilog, and below is the Verilog code, the testbench and the waveform that I am getting,
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Different outputs for RTL and gate level netlist simulations for a latch used in clock gating
I am trying to implement clock gating logic manually using a latch and an AND gate as shown in the figure.
The latch has an enable (en) and a done signal which are ...
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What to do when a Verilog state machine simulation doesn't reflect the signals?
I'm working on a Verilog project using ModelSim, and I've created a testbench to simulate the behavior of a module called Elevator_FSM, which models an elevator's operation.
My goal is to assign ...
- 61
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Analyzing unexpected output from Verilog bit unpacking and reassembly logic
I'm working on a Verilog task that rearranges bits from a 312-bit word into a new 312-bit format using 8-bit temporary storage (temp[39]). Below is a simplified ...
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How blocking assignment affect non-blocking assignment in Verilog?
module t;
reg a;
initial a <= #4 0;
initial a <= #4 1;
initial $monitor ($time,,"a = %b", a);
endmodule
Output of above Verilog code is:
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463
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Why is Vivado connecting this reset to the CE pin when the R pin is available?
Vivado is connecting up the reset signal through a LUT to the CE pin of the FDRE, even though the R pin is available. This is a 2k signal, and it's using up 2k LUTs to do this, unnecessarily. Any ...
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Vivado Simulation Bug for 4 bit asynchronous ripple counter
I am currently learning Verilog and tried to build an asynchronous counter using T flip flops.
But, during the simulation, my most significant three bits become one without any clock signal from the ...
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SystemVerilog's $fdisplay/$fopen don't create a file
I am trying to save the results of simulation to a file from a testbench. Here is the problematic snippet:
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Clocking block skew in interface modport
For the code: EDA Playground
In the interface code:
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How can I make sure the signal is not X when accessed?
I just found a bug in hardware that wasted hours of my time, and I never thought about it.
I have something like that:
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