Ultra low inductance trace - disadvantages?

That is correct, the capacitance is higher.

It does not interfere, however.

Most generally speaking, we construct a parallel-plate transmission line, with characteristic impedance \$Z_0 = \sqrt{\frac{\mu}{\epsilon}} \frac{d}{w}\$ (for height d and width w, w ≫ d so that fringing can be ignored), velocity factor \$c_0 = \frac{1}{\sqrt{\mu_r \epsilon_r}}\$, and so capacitivity \$C_0 = \frac{1}{Z_0 c_0 c} \$ and inductivity \$L_0 = \frac{Z_0}{c_0 c} \$. Which have units of F or H per length, so, multiply by line (physical) length to get F or H total, as the low-frequency equivalent parameter. And, of course, we don't usually have magnetically-loaded laminates so \$\mu_r = 1\$ but \$\epsilon_r\$ is of importance.

For any reasonable length of transmission line used for gate connections here, you will find the total capacitance contribution is tiny -- dozens of pF at worst. The gate capacitance itself (or equivalent including gain and nonlinearity) might be some nF, 10s even.

We can approach the gate circuit as a lumped-equivalent network. We have some shunt C at the end (the gate itself), series R_G consisting of internal gate resistance, added external resistance, and the driver's internal or equivalent resistance. We have the connection between driver and gate, contributing series inductance L. For given L and C, the characteristic impedance of the resulting series-resonant tank is \$Z_R = \sqrt{\frac{L}{C}}\$. When this impedance is lower than \$Z_0\$ of the transmission line, the line manifests as series inductance; when higher, shunt capacitance.

Generally speaking, it is very difficult indeed to get \$Z_0\$ low enough, at the board level, that trace capacitance matters in the slightest for switching purposes.

A trace of 10mm width, 0.1mm height and \$\epsilon_r = 4\$ gives \$Z_0 = 1.9 \Omega\$ or thereabouts. That's such a ponderously wide trace that you'll have a hard time even connecting it into a gate and driver (notice the tapered sections between pin/pad and the bulk of the trace/pour are necessarily narrower, thus higher \$Z_0\$ too).

Meanwhile, we might have L of 10nH and C of 10nF, or \$Z_R = 1\Omega\$ easily enough. These would be typical figures for a driver IC adjacent to the transistor (within a few mm), and certainly we cannot have a \$Z_0\$ nearly so low in such circumstances. So it's okay to treat it as lumped inductance.

The same analysis applies to the power switching (drain) path, which shows us for example the necessity of DFN packages for these transistors -- a D2PAK, let alone TO-220 or the like, would be ludicrous at such switching speeds, and impedances -- where 10nH is present in the package itself, regardless how we place and orient them on the PCB, regardless how much interleaving and plane width we use underneath! Truly the best we can do is place a pair of DFNs and bypass caps all in a pile (possibly on both sides of the board), and hope that we get low enough (single digit nH) to survive the switching speed these things are capable of. And if not, then we can subdivide the circuit into parallel channels, where each individual inverter has realistic capacity (given its parasitics and switching impedance), which also gives us the opportunity to apply multi-phase interleave to reduce input and output ripple currents.

Though, despite all that, there are some companies making GaN-hybrid transistors in TO-220 and the like, for backwards compatibility more or less; sort of in the interim, while silicon-based controllers and existing applications still dominate (i.e., 8-15V gate drive). While these can hardly harness the full capability of the GaN chip within (primarily for the above reason, though there are others), the improvements on switching and conduction loss may prove worthwhile as an easier upgrade path.

As long as we're on the topic, it's worth mentioning the same applies again to transformer design. Generally speaking, anywhere we have adjacent conductors carrying signals, we have some manner of transmission lines, and impedance and frequency response or time constants associated with them. I won't go into excruciating detail when there's not even an example to start with here, but merely to drop the hint that, indeed, we can approach transformer design exactly the same way. In that case, winding (wire) length matters, and the winding geometry (relative wire orientation between pri/sec; interleaving); and the consequences are leakage inductance and stray capacitance. If we were designing gate drive transformers, this would be directly applicable, leakage adding to the stray loop inductance; for isolated converters, we see that isolation capacitance and stray inductance are necessarily linked, and so we must consider both in any design tradeoffs we might make.